In a standard form of well known integrated circuit random access memory (RAM) structure comprising a plurality of memory cells, for example 1024 memory cells in a 32 .times. 32 matrix, each memory cell includes three transistors, i.e., a storage transistor, a write transistor, and a read transistor. The drain to source circuit of the read transistor is connected in series with the drain to source circuit of the storage transistor and the drain to source circuit of the write transistor is connected to the gate of the storage transistor. With an X-select signal logically ANDED with a write signal and applied as a decode signal to the gate of the write transistor, the write transistor is turned on and establishes a low impedance input path from a charging voltage source to the gate of the storage transistor. This creates a stored charge in the inherent capacitor existing between the gate and the substrate region of the storage transistor, this stored charge at the gate node providing the desired memory storage in the form of a logic one or zero. With the turn-on signal removed from the gate of the write transistor, the charge will remain stored on this node for a suitable period of time, for example a 2 millisecond life time. This stored charge state may be read out from the storage transistor by an ANDED X-select and read signal applied to the gate of the read transistor, the read transistor thus being turned on and establishing a low impedance path from the drain to source circuit of the memory transistor to the date output line of the storage cell.
By establishing a stored charge in the gate circuit of the storage transistor in selected ones of the plurality of memory cells while omitting such a stored charge from the storage node of the storage transistors of the remaining cells, the programmed two logic states, i.e., a zero or a one, may be selectively stored in the memory structure.
Because of the two millisecond life time for the charge stored in the gate node of the storage transistor, it is necessary that the stored information be cyclically enhanced at least once within every two millisecond life time of the charge. For this purpose a feedback circuit is completed from th output of the memory cell via the read transistor and through a sense amplifier to the input circuit of the cell, i.e., to the drain to source circuit of the write transistor, and this circuit is established once within every such life time to re-enhance the storage charge on the gate node of the storage transistor. By thus cyclically re-enhancing the stored charges in the individual memory cells, e.g., once every 64 microseconds, the logic information stored in the memory structure may be maintained for long periods of time. The logic stored in any one cell within the multicell structure may be rapidly changed without affecting the other cells by writing a different signal input into the storage transistor of the one cell via the associated write transistor. Thus, the program stored in a memory cell array may be changed by changing the storage state of just one cell or any number of selected cells while retaining the remainder of the memory cells in their present logic state. Because of this ease of storage cell change, the dynamic RAM circuit lends itself readily to use in situations where slight modifications may be desired from time to time in a stored logic program. If, however, the power to the circuit should be interrupted even only momentarily, all of the logic information stored in the memory cells will be lost due to the inability to re-enhance the stored charges within the two millisecond life time.
Another well known form of integrated circuit matrix type memory cell structure is the non-volatile read only memory (ROM) which comprises a two transistor cell structure including a floating gate storage or memory transistor and a read-write transistor with its drain to source circuit connected in series with the drain to source circuit of the floating gate storage transistor. By applying a high voltage pulse via the drain to source circuit of the read-write transistor, which may be turned on by a logically ANDED select X and write signal applied to the gate thereof, to the drain to source circuit of the storage transistor, a charge may be stored in the floating gate of the storage transistor. This stored charge in the floating gate has a half-life time of 10 years and is thus, for all practical purposes, a permanent storage which need not be periodically enhanced as is the case with the RAM memory cell. The state of the storage transistor may be read out at any time by a decode signal comprising an X signal logically ANDED with a write signal applied to the gate of the write-read transistor which establishes a low impedance path between the drain to source circuit of the storage transistor and the output circuit of the memory cell. A typical program time for a ROM is about 100 milliseconds and the erase time for the memory structure using ultraviolet light is about five minutes. During the erase, all of the cells are erased simultaneously so that there is no selective erase and rewrite on one or more of the cells. Because of the long program time and the long erase time, as well as the bulk erase, the non-volatile ROM memory cell structure is not useful in applications where the stored program is desired only for short periods of time with minor changes to be made in the stored program at frequent time intervals. However, the ROM structure lends itself to use where power failures may be expected since the program stored on a ROM structure will remain intact even when the power to the circuit is interrupted.